The JTAGMaster Tester and Programmer is a fully integrated solution for the configuration and diagnosis of Programmable Logic Devices (PLDs). This unit includes :
A boundary-scan tester to arbitrarily observe individual pins and therefore determine their functionality. This information can be saved in customisable test procedures which can also include pictures and datasheets. EXTEST mode is also available to manually change the state of pins and trace the effect(s) on the other device(s) in the chain. Scan Check is a multi-license software to run boundary scan checks on multiple stations.
A programming interface designed to handle industry standard JAM STAPL files (Standard Test And Programming Language) and SVF files (Serial Vector Format) to send programming instructions as well as testing functions to the device. ABI uses the JTAG Standards (Joint Test Action Group, compatible with IEEE1149.1) which ensures compatibility between all compliant ICs.
The JTAGMaster is also capable of programming EEPROM devices using external adapters. Standard brinary files are supported and can also be modified in the device buffer window. A wide range of EEPROM devices are present in the library which can be easily modified by users. The following protocols are supported by the JTAGMaster :
- Serial Peripheral Interface (SPI)
- Inter-Integrated Circuit (I²C)
- Microwire (μwire)
As a product, the JTAGMaster In-System and Standalone Programmer is also available.
Please click here to view the complete brochure.
The JTAGMaster Tester and Programmer is designed to work with ABI’s bespoke software – a multiple purpose platform which enables users to freely configure test procedures and instruments. Integrated functions are also available to the user to automatically learn the device status, provide pin-to-pin comparison and information as well as use some reporting facilities. The internal library can be updated through BSDL files available from manufacturers’ websites (see below).
With its ability to both test and program PLDs, this new ABI product allows users to verify the functionality of a device, download a bespoke program to a device or even re-test the device after it has been programmed !
A complete training package for the JTAGMaster is also available – please click here for more information.
A more detailed presentation video is available here.
Boundary Scan Description Language (BSDL)
Boundary Scan Description Language (BSDL) is a subset of VHDL that is used to describe how JTAG (IEEE 1149.1) is implemented in a particular device. For a device to be JTAG compliant, it must have an associated BSDL file. These files are often available for download from manufacturers’ websites (see below). JTAG systems uses the information contained in a BSDL file to work out how to access a device in the JTAG chain. BSDL files contain the following elements:
- Entity Description: Statements naming the device or a section of its functionality.
- Generic Parameter: A value such as a package type. The value may come from outside the current entity.
- Port Description: Describes the nature of the pins on the device (input, output, bidirectional, linkage).
- Use Statements: References external definitions (such as IEEE 1149.1).
- Pin Mapping(s): Maps logical signals in the device to physical pins.
- Scan Port Identification: Defines the pins used on the device to access the JTAG capabilities.
- Instruction Register Description: The signals used for accessing JTAG device modes.
- Register Access Description: Which register is placed between TDI and TDO for each JTAG instruction.
- Boundary Register Description: List of the boundary scan cells and their functionality
Download BSDL files for your JTAG components
- Boundary scan testing
- Integrated JAM/SVF Player for programming
- Automatic detection of JTAG chains
- Automatic training function
- JTAG/IEEE 1149.1 compatible
- USB2.0 compatible
- Built-in power supply (1.8 to 3.3 Volts)
Comprehensive Training Package (optional)